Quantum annealing vs. gate-based: what can each one do?

TL;DR. Quantum annealing and gate-based quantum computing share the word "quantum" and little else a buyer should act on. An annealer is one fixed algorithm built as a physical machine: it relaxes toward low-energy states of an Ising problem you write into its couplers — 4,400+ physical qubits shipping today (D-Wave Advantage2, generally available May 20, 2025). A gate-based computer is a programmable machine: it runs arbitrary circuits — Shor, Grover, chemistry — at 100–1,121 physical qubits. The equivalence theorem people quote ("adiabatic = gate model") covers an idealized cousin of annealing, not the hardware that ships. Neither paradigm has a measured end-to-end advantage on a useful problem as of September 2026 — and the sharpest fresh datapoint is that the annealing company itself began building a gate-model machine this year.

Status as of: September 1, 2026.

What is quantum annealing?

Quantum annealing was proposed by Kadowaki and Nishimori in 1998 (Phys. Rev. E 58, 5355): start a transverse-field Ising system in an easy superposition, then slowly turn the problem couplings on and the transverse field off, letting quantum fluctuations help the system settle into a low-energy configuration. The machine does not execute instructions — the physics is the algorithm, cast in hardware once, at design time.

That has two immediate consequences. First, the input format is fixed: an annealer accepts exactly one kind of question — minimize an Ising/QUBO energy function — so every business problem must first be translated into that shape, with the translation costs and penalty-knob traps we covered in our Hamiltonian explainer. Second, the run is analog: there are no discrete steps to verify, no circuit to audit mid-flight, and — unlike the gate model — no demonstrated scheme for error-correcting an annealing run. Vendors mitigate with multiple reads, spin-reversal transforms and calibration, but nothing equivalent to a logical qubit exists for analog annealing today (Albash & Lidar, Rev. Mod. Phys. 90, 015002, 2018).

What is the gate model?

The gate model is the quantum analogue of a programmable processor: qubits hold amplitudes, and a circuit — a scheduled sequence of gates chosen per problem — rotates those amplitudes so wrong answers interfere away (our qubit primer covers the mechanics). Every named algorithm with a proven speedup — Shor, Grover, quantum simulation, the short honest list — is a gate-model program. So is the fault-tolerance roadmap: logical qubits assembled from physical ones, the physical-to-logical ratio improving by measured demonstration. None of that library runs on an annealer, because an annealer has no instruction set to run it on.

Isn't annealing provably equivalent to the gate model?

This is where the marketing and the mathematics part ways, so it deserves precision. There is a celebrated theorem: Aharonov et al. (SIAM J. Comput. 37, 166, 2007) proved that adiabatic quantum computation — evolve slowly enough, stay in the ground state — can simulate any quantum circuit with polynomial overhead. Universal, full stop.

But the theorem's machine is not the machine that ships. Three gaps, each documented in the standard references:

The stoquastic restriction is the load-bearing word. Stoquastic Hamiltonians (Bravyi, DiVincenzo, Oliveira & Terhal, arXiv:quant-ph/0606140, 2006) have no "sign problem," which is precisely the property that lets classical quantum-Monte-Carlo methods track them efficiently in many regimes — one structural reason the classical side keeps catching up to annealing claims. A transverse-field Ising annealer lives entirely inside that restricted class. So the honest summary is: ideal adiabatic computation is universal; the annealers you can rent are not. When a pitch cites the theorem on behalf of the hardware, it is quoting a different machine's diploma.

What can each machine actually do today?

The qubit-count comparison deserves its own warning: 4,400 annealing qubits and 1,121 gate qubits are not the same unit. Annealing qubits carry one fixed interaction pattern at analog precision; gate qubits carry arbitrary programs at circuit depth. Comparing the two headline numbers is exactly the vendor-metric trap this series keeps flagging.

What does the measured record say?

Three entries, each with its own fine print. First, the strongest annealing claim on record: King et al. (Science, March 2025) reported beating classical simulation on spin-glass dynamics — quantum simulation of magnetic materials, not optimization. Classical tensor-network methods matched substantial parts of it on a laptop within days as a preprint, published in Science 392, 868 on July 21, 2026; D-Wave published a detailed response ("Result Stands," May 26, 2026) maintaining that the hardest instances and higher-order observables remain out of classical reach. The dispute is open — we re-checked this week and found no adjudication in either direction as of September 1, 2026. Both sides are linked below; our reproducibility post walks through the episode. None of this is an accusation: the claim published its data, the counterattack ran on it, and the rebuttal is public — the system working as it should.

Second, the strongest annealing optimization number of 2025: a benchmarking study (Kim et al., npj Quantum Information, 2025) reports a hybrid quantum-annealing pipeline solving a 10,000-variable dense QUBO in 0.0855 s where a simulated-annealing baseline took 561 s — roughly 6,561×. Read the authors' own fine print before repeating the number: the winning solver is a hybrid whose classical component is proprietary and undisclosed, pure annealing "struggles with large dense problems," and timing excludes queue overhead. A speedup attributed to a black box that is part classical is a claim about the box, not yet about the quantum paradigm inside it — the same audit rule as ever: strongest classical baseline, same instance, same rules.

Third, the long baseline: when a neutral methodology was imposed on annealing hardware (Rønnow et al., Science 345, 420, 2014 — "Defining and detecting quantum speedup"), the measured scaling advantage was absent once instance selection and budget were controlled. And in applied routing work, mature classical solvers remain ahead on production-shaped problems. The scoreboard this series maintains does not move: measured end-to-end advantage on a useful problem, either paradigm, zero.

The freshest datapoint: the annealing company is building a gate machine

On June 1, 2026, D-Wave — the only company that ever bet purely on annealing — published a gate-model roadmap: superconducting dual-rail qubits, 17 physical in 2026, 49 in 2027, 181 in 2028, 10 logical qubits targeted for 2030 and 100 logical for 2032, with a claimed error-suppression factor target of Λ = 10. Every date there is a roadmap, and roadmaps are the interested party's optimistic target — the track record on such dates is not bad, it is empty. But the capital allocation itself is data of the best kind: the vendor with the deepest annealing expertise on Earth has concluded that the universal algorithm library requires a gate machine. That is the cleanest available answer to this post's question, stated by the party with the least incentive to say it — and it is a strategy any observer can read from public filings, not a leak.

What we know / what we don't know

We know: annealing and gate computing are different machines with different job descriptions — one fixed analog algorithm versus a programmable instruction set (Kadowaki & Nishimori 1998; Aharonov et al. 2007). We know the universality theorem does not transfer to stoquastic, open-system hardware (Bravyi et al. 2006; Albash & Lidar 2018). We know the shipping scales: 4,400+ annealing qubits, ~100–1,121 gate qubits, logical-qubit demos only on the gate side. We know neither paradigm has a measured end-to-end win on a useful problem, and that D-Wave itself now builds both.

We don't know: whether annealing retains any scaling edge on its native problems once the spin-glass dispute resolves — it is open, and "open" is a state, not a verdict. Whether non-stoquastic or diabatic annealing designs can escape the classical-simulability window — active research, no shipped hardware. Whether hybrid speedups like the 6,561× survive disclosure of the proprietary classical component and a matched-budget strongest baseline. Whether any of D-Wave's dual-rail dates land — no roadmap date in this industry has yet been graded. And there is no shared protocol for benchmarking an annealer and a gate machine on the same instance under the same rules — so even the comparison in this post inherits each side's own metrics.

Our own sealed runs (the V-0012 series) are gate-paradigm QAOA simulations and quantum walks; we have no measurements on annealing hardware and claim none here.

Sources

• Kadowaki & Nishimori, Phys. Rev. E 58, 5355 (1998)
• Aharonov et al., SIAM J. Comput. 37, 166 (2007)
• Albash & Lidar, Rev. Mod. Phys. 90, 015002 (2018)
• Bravyi, DiVincenzo, Oliveira & Terhal, arXiv:quant-ph/0606140 (2006)
• D-Wave, Advantage2 general availability (May 20, 2025)
• The Quantum Insider, D-Wave gate-model roadmap (Jun 1, 2026)
• King et al., Science (Mar 2025)
• Tindall et al., Science 392, 868 (Jul 21, 2026)
• D-Wave, "Result Stands" (May 26, 2026)
• Kim et al., npj Quantum Information (2025), arXiv:2504.06201
• Rønnow et al., Science 345, 420 (2014)

Rosetta Q publishes verdicts with reproducible raw data. This is educational content, not a product claim.