What does NVQLink actually connect between GPUs and QPUs?

TL;DR (status as of October 17, 2026): NVQLink is NVIDIA's «open system architecture for tightly coupling the extreme performance of GPU computing with quantum processors», announced October 28, 2025 at GTC Washington (nvidianews.nvidia.com). It is not a cable and not a product with a price: it is RDMA over Converged Ethernet as transport, an open-source FPGA core on the quantum-controller side, and a CUDA-Q runtime call — cudaq::device_call — in software (NVIDIA developer blog, November 17, 2025). What is measured today: a 3.84 µs mean loopback latency on NVIDIA's own bench, with no QPU in the loop; a 67 µs median decode of Quantinuum Helios data that cut a logical error rate 5.4×; and decoder benchmarks at 2.1–2.3 µs per round (sources below). What the public record does not yet contain: a single production deployment running closed-loop quantum error correction through NVQLink. Rosetta Quantum separates the architecture from the adoption press releases.

What is NVQLink?

An architecture, not a device. NVIDIA's launch release defines NVQLink as «an open system architecture for tightly coupling the extreme performance of GPU computing with quantum processors», announced with support from 17 QPU builders, five controller makers — Keysight Technologies, Quantum Machines, Qblox, QubiC and Zurich Instruments — and nine U.S. national laboratories (nvidianews.nvidia.com, October 28, 2025). The same release contains zero performance numbers: no latency, no bandwidth, no spec sheet. Access is by sign-up, and the forward-looking disclaimer states products «will be offered on a when-and-if-available basis» (nvidianews.nvidia.com, October 28, 2025). The numbers arrived three weeks later, at SC25.

What one actually assembles, per NVIDIA's technical post (developer.nvidia.com, November 17, 2025), is four layers. Transport: the real-time interconnect «is implemented using RDMA over Converged Ethernet (RoCE)» — standard datacenter Ethernet, which NVIDIA notes already runs 400 Gbit/s links. Controller side: the quantum system controller's pulse processing units (FPGAs or RFSoCs) connect through an FPGA core that NVIDIA describes as freely available, requiring no disclosure of the vendor's proprietary firmware. Host side: a GPU node with an RDMA-capable NIC — the published demo used an RFSoC, an Arm host, an RTX PRO 6000 Blackwell GPU and a ConnectX-7 NIC, «commercially available components» (developer.nvidia.com, November 17, 2025). Software: CUDA-Q, where one program holds both the quantum kernel and the classical callback.

What is measured, as of October 2026?

Three families of numbers, and each comes with its own asterisk. First, the link itself: NVIDIA measured an end-to-end RoCE loopback — FPGA to GPU and back — at 3.84 µs mean, 0.035 µs standard deviation and 3.96 µs maximum over 1,000 samples (developer.nvidia.com, November 17, 2025). That is the measurement behind the «<4 microseconds» figure that circulates; it was taken point-to-point on a bench, with no QPU in the loop. The 400 Gb/s GPU-to-QPU throughput and 40 petaflops of FP4 compute quoted at SC25 are platform-class figures, not loopback measurements (nvidianews.nvidia.com, November 17, 2025).

Second, a decode of real quantum data within a real budget: NVIDIA and Quantinuum ran a qLDPC decode — Bring's code, 8 logical qubits in 30 physical, BP+OSD decoder — on a GH200 host against Helios data, with a 67 µs median decoding time and a logical error rate of 0.925±0.38% after three rounds of correction versus 4.95±0.67% before, a 5.4× improvement (developer.nvidia.com, November 17, 2025). SC25 framed the same number against the machine's clock: 67 µs is about 32× inside the «two-millisecond window» Helios allows (nvidianews.nvidia.com, November 17, 2025). One caution our ledger adds: a trapped-ion machine is a patient patient — Helios averages ≈55 ms per circuit layer, as our Helios spec sheet documented — so a 2 ms decode budget is the generous end of the problem.

Third, decoder benchmarks without hardware: CUDA-Q QEC 0.6 added two real-time decoder pipelines and benchmarked them at 2.1 µs per round (fast CNN pre-decoder + PyMatching) and 2.3 µs per round (accurate variant) on a distance-13 surface code at physical error rate 0.003, with the pre-decoders on a B300 GPU and PyMatching on a Grace CPU (developer.nvidia.com/cuda-quantum, April 14, 2026). Those runs decode syndromes; they do not control a quantum computer.

What is CUDA-Q, and what does it actually add?

CUDA-Q is the software half of the answer: NVIDIA's open-source platform — Apache-2.0 licensed, C++ and Python — for programs that mix quantum kernels and classical code (github.com/NVIDIA/cuda-quantum, accessed October 17, 2026). What NVQLink adds to it is one intrinsic: cudaq::device_call lets a quantum kernel invoke a function on the GPU or CPU and receive the result back within microseconds (developer.nvidia.com, November 17, 2025). That call is the actual «connection» in the headline: a programming contract between a running circuit and a classical processor, with the RoCE fabric underneath it. The fine print is printed by NVIDIA itself: in CUDA-Q QEC 0.6, the real-time dispatch path is C++ only — «there is no Python binding for the real-time dispatch path» (developer.nvidia.com/cuda-quantum, April 14, 2026).

Who has actually run something through it?

The demo record, one row per actor, with what each run did and did not include:

Read the table's fourth column from top to bottom and the pattern is the honest definition of where NVQLink stands: the fastest measured number has no quantum computer in it, the run with real quantum data is a decode demo, the live end-to-end run published no numbers, and the newest demo (October 14, 2026) ran offline on synthetic data. The adoption list — RIKEN, Jülich, CINECA, GENCI, the UK's NQCC, KAUST and ten more centers joining the nine U.S. national laboratories — is written in the future tense: Quantinuum's Helios «will be integrated», centers «are adopting» (nvidianews.nvidia.com, November 17, 2025). Commitments of that size are a real signal about where the industry expects control systems to go. They are not yet measurements.

How do you read an «NVQLink-ready» claim?

With the test our hybrid-systems explainer proposed: ask which side does the work. In every NVQLink result published so far, the measured work is classical — moving syndromes and decoding them. That is not a gotcha; it is the design. Error-correction decoding is a classical real-time computing problem, and whether GPUs can hold microsecond deadlines at scale is exactly what these demos probe. The quantum side enters through one number the vendor must state: the machine's own decode budget. Helios tolerates ≈2 ms (nvidianews.nvidia.com, November 17, 2025). A superconducting processor produces a syndrome round every 1.1 µs — Google's below-threshold experiment reported an average real-time decoder latency of 63 µs at distance 5 just to keep pace (arXiv:2408.13687, 2024) — a clock roughly 1,800× faster than the trapped-ion budget (2 ms against 1.1 µs; our arithmetic, declared). On that clock, link latency (3.84 µs measured) plus decode time (2.1 µs per round, benchmarked) stops being a rounding error, which is why the ratio arithmetic and the architecture trade-offs decide whether this link closes the loop. The checklist, then: Was there a QPU in the loop, or synthetic data? Is the latency a measurement or a design target? Is there a logical error rate before and after? And is the whole loop inside the machine's own budget — not a budget borrowed from a slower architecture? Four questions, all answerable from a vendor's own PDF, in the spirit of our claim-credibility checklist.

What we don't know

• Whether 3.84 µs survives a loaded fabric. The measurement was a point-to-point loopback on a bench (developer.nvidia.com, November 17, 2025). Jitter across a production datacenter switch fabric under load, with congestion from classical traffic, has no published NVQLink measurement that we found.
• What Quantum Machines measured. The September 2026 end-to-end run is the most complete demonstration on record — a physical QPU, GPUs and a PPU in one CUDA-Q program — and its public coverage contains no latency and no error-correction numbers (quantumcomputingreport.com, September 14, 2026).
• Whether the superconducting loop closes. The IQM + Zurich Instruments demonstrator on a 20-qubit superconducting chip is the stated test of real-time QEC through NVQLink at microsecond budgets (quantumcomputingreport.com, March 2026); as of October 17, 2026 we found no published logical error rate from it.
• The exact wiring of the Quantinuum 67 µs demo. NVIDIA's post gives code, decoder, host and median time; whether the decode ran inside a live Helios control loop or against streamed data is not detailed at the level we would need to reproduce it (developer.nvidia.com, November 17, 2025).
• Price, SKU and dates. No general-availability date, no price, and adoption timelines for the 15 centers are unstated; the launch disclaimer says «when-and-if-available» (nvidianews.nvidia.com, October 28, 2025).

Sources

• NVIDIA — «NVIDIA Introduces NVQLink — Connecting Quantum and GPU Computing for 17 Quantum Builders and Nine Scientific Labs» (2025-10-28) — nvidianews.nvidia.com
• NVIDIA Developer Blog — «NVIDIA NVQLink Architecture Integrates Accelerated Computing with Quantum Processors»: RoCE transport, open FPGA core, 3.84 µs loopback, Quantinuum 67 µs demo (2025-11-17) — developer.nvidia.com
• NVIDIA — «World's Leading Scientific Supercomputing Centers Adopt NVIDIA NVQLink to Integrate Grace Blackwell Platform With Quantum Processors» (2025-11-17) — nvidianews.nvidia.com
• NVIDIA Quantum — «CUDA-Q QEC 0.6 Enables Real-Time QEC with NVQLink»: decoder pipelines, 2.1–2.3 µs per round, C++-only real-time path (2026-04-14) — nvidia.github.io
• Quantum Computing Report — «Quantum Machines Demonstrates Live End-to-End CUDA-Q Program Execution via NVIDIA NVQLink» (2026-09-14) — quantumcomputingreport.com
• Quantum Computing Report — «IQM and Zurich Instruments Develop Real-Time QEC via NVIDIA NVQLink» (March 2026) — quantumcomputingreport.com
• Quantum Computing Report — «Alice & Bob Demonstrates GPU Decoding for LDPC-Cat Codes via NVIDIA NVQLink» (2026-10-14) — quantumcomputingreport.com
• GitHub — NVIDIA/cuda-quantum: Apache-2.0, C++ and Python (accessed 2026-10-17) — github.com
• Google Quantum AI — «Quantum error correction below the surface code threshold»: 1.1 µs cycle, 63 µs real-time decoder latency at distance 5, arXiv:2408.13687 (2024) — arxiv.org
• Rosetta Quantum — related ledger entries: #82 Helios, measured vs promised · #44 hybrid systems, who does the work · #33 logical qubits and the ratio · #20 superconducting vs trapped ion · #31 the claim-credibility checklist · #62 quantum and generative AI

Rosetta Quantum publishes verdicts with raw, reproducible data. This is educational content, not a product claim. Quantum, independently measured.