What happened to cat qubits and bosonic error correction?

What is a cat qubit and why does its noise bias matter?

A cat qubit stores quantum information in two opposed coherent states of a superconducting resonator, instead of the two energy levels of a transmon. The design buys a deliberately lopsided error profile: bit-flip errors are suppressed exponentially as the number of photons in the resonator grows, while phase-flip errors get worse roughly in proportion to that same photon number (PostQuantum, Sep 26, 2025). The bet is that killing one of the two error types in hardware lets the error-correcting code concentrate on the other — a 1D repetition code or an LDPC code instead of the 2D surface code, with far fewer physical qubits per logical qubit.

That bet has a published price tag. The LDPC-cat architecture paper by Alice & Bob and Inria researchers (Ruiz et al., arXiv:2401.09541, Nature Communications 2025) estimates 100 logical qubits on a 758-cat-qubit chip at a total logical error rate ≤10⁻⁸ per cycle — assuming a physical phase-flip error probability of about 0.1%. Every number in this post should be read against that assumption: the architecture is a paper, and its 0.1% input is a target, not a measurement. Rosetta Quantum keeps the same yardstick here that it applied to logical-qubit demonstrations across vendors: measured numbers first, promises in the future tense.

What is actually measured on cat and bosonic hardware?

The measured record is real and, on one axis, extraordinary. Alice & Bob published bit-flip times exceeding 10 seconds in Nature (Réglade et al., May 2024) and reported about 430 seconds on its Boson 4 chip later in 2024 (both via the Quantum Zeitgeist profile, Jul 17, 2026). On September 25, 2025 the company announced a cat qubit whose mean bit-flip time is roughly one hour — 41 flips observed over 61 hours, a mean of ≈44 minutes with a 95% confidence interval of 33 to 60 minutes (PostQuantum, Sep 26, 2025). That result is a company announcement, not a peer-reviewed paper, and it came with the other side of the ledger attached: the same device showed a phase-flip timescale of about 0.4 microseconds and a Z-gate fidelity just above 94%. The bias is not a side effect — it is the product. Bit-flips were measured in minutes; phase-flips were measured in microseconds; both numbers are real.

AWS put the same trade-off through a full repetition code. Its Ocelot chip (Nature, Feb 27, 2025; analysis) combines 5 cat qubits and 4 transmon ancillas; physical bit-flip times approach one second and phase-flip times sit near 20 microseconds. The distance-5 code delivered a total logical error rate of about 1.65% per cycle versus about 1.7% at distance 3 — nearly flat, because residual bit-flips cap the total even as the code suppresses phase-flips exponentially with distance. Ocelot realizes one logical qubit, runs no algorithms, and demonstrates no logical-to-logical gates.

Nord Quantique, the bosonic-code team closest to this family, measured a 14% lifetime extension on a single GKP-encoded qubit with autonomous error correction and no extra physical qubits (arXiv:2310.11400, announced February 2024). In mid-2025 it ran a two-mode Tesseract-code logical qubit through 32 consecutive error-correction rounds with no measurable decay — while discarding about 12.6% of runs in which faults were detected (PostQuantum profile). In July 2026 it reported state-preparation-and-measurement errors below 0.1% on a single-mode grid-state qubit using a repeat-until-success protocol (The Quantum Insider, Jul 13, 2026; arXiv:2607.06718). Both of the strongest Nord Quantique results lean on post-selection: discarding bad runs is legitimate physics and honest reporting, but an operating computer will have to correct errors, not discard them.

What do the roadmaps promise — and in what tense?

Everything at scale is still written in the future tense, and Rosetta Quantum will keep it there. Alice & Bob's roadmap will culminate in “Graphene,” a 100-logical-qubit machine targeted for 2030; the company states that the one-hour result clears the 13-minute bit-flip threshold its 2030 design will need, and its cumulative funding stood near €130 million as of April 2026, with an NVIDIA NVentures investment added in May 2026 (Quantum Zeitgeist, Jul 17, 2026). Nord Quantique's public roadmap targets 100 logical qubits by 2028, while its press material describes a “clear path” to a 100-plus-logical-qubit machine by 2029 — both dates coexist in its own communications (PostQuantum profile). Its flagship efficiency claim — that ≈1,000 logical qubits will factor an 830-bit RSA number in about an hour on ≈120 kWh, versus ≈280,000 kWh for a classical cluster — is a company projection, not a measurement. The same goes for AWS: Ocelot's “up to 90%” error-correction overhead reduction is a projection tied to a forthcoming scaling paper.

The classical half of the promise is also unfinished. Decoding an LDPC-cat code in real time is a hard classical problem — the subject of our decoder explainer. On October 13, 2026 Alice & Bob and NVIDIA reported the first GPU decoding of LDPC-cat codes over the NVQLink connection we examined in a previous verdict — a feasibility proof-of-concept on synthetic data, with no published latency or throughput figures, following a March 2026 CUDA-Q run that took 1 hour 57 minutes on simulated syndromes (Quantum Zeitgeist, Oct 13, 2026). Real-time decoding at the cadence a 758-cat chip will demand has not been demonstrated.

What did DARPA's benchmarking funnel say about bosonic machines?

As of October 7, 2026, no cat or bosonic team sits in the final stage of the only benchmarking funnel with independent government verification. DARPA's Quantum Benchmarking Initiative — our explainer — now has six teams in Stage C: Microsoft and PsiQuantum (added February 2025 via the predecessor program) plus Atom Computing, Diraq, IBM and IonQ (added October 7, 2026) (PostQuantum, Oct 2026). Nord Quantique did reach Stage B as one of 11 teams on November 6, 2025, with up to $15 million per team (Quantum Computing Report); Alice & Bob took part in Stage A and was not on that Stage B list. DARPA describes advancement as staggered, so absence from Stage C is not a published rejection — but the scoreboard today reads: six finalists, zero bosonic.

What we don't know

We don't know whether the one-hour bit-flip protection survives two-qubit operations — Alice & Bob itself lists them as untested and planned for its Helium chip. We don't know whether Nord Quantique's post-selected results (12.6% of runs discarded; repeat-until-success preparation) will translate into always-on correction at speed. We don't know whether any hardware today meets the ≈0.1% phase-flip input that the 758-cat estimate assumes, at the photon numbers that assumption requires — the measured phase-flip timescales published so far are fractions of a microsecond to tens of microseconds. We don't know why specific teams are absent from QBI Stage C, because DARPA has not said. And we don't know the real-time latency of LDPC-cat decoding on GPUs, because the only demonstration so far ran on synthetic data.

Rosetta Quantum will publish a re-verdict when Alice & Bob reports two-qubit results, when Nord Quantique publishes multi-logical-qubit operations, or when a bosonic team enters QBI Stage C — whichever lands first.

Rosetta Quantum publishes verdicts with raw, reproducible data. This is educational content, not a product claim.